The present invention relates to an image processing apparatus processing a plurality of functions; and especially to an image processing apparatus and an image processing system using the apparatus in which a plurality of functions are efficiently executed by using a shared memory as both a main memory for a CPU and an image memory.
As a first example of a conventional image processing technique for processing an image at a high speed, for example, as disclosed in Japanese Patent Application Laid-Open Hei 5-307531, the composition of an image processing apparatus with a plurality of image memories exclusively used for an image processing unit is shown in FIG. 2A. In this image processing apparatus, the feeding of data to be processed from one of the image memories to the image processing unit can be performed in parallel to storing the processed data to the image memory, which can improve the speed in image data processing. Also, even if the image processing unit is substituted with an image input/output unit, it is possible to access the image memory in parallel while simultaneously performing an image input task and an image output task. That is, reading image data out of the image memory can be performed in parallel to writing in image data into the image data.
Moreover, as a second example of a conventional image processing technique for processing an image at a high speed, for example, as disclosed in Japanese Patent Application Laid-Open Hei 5-120239, the composition of an image processing apparatus with a shared memory provided for a CPU as a main memory and for an image processing unit as an image memory is shown in FIG. 2B. In this image processing apparatus, since the shared memory is used by the CPU, the image processing unit, and the image input/output unit, it is possible to reduce the amount of hardware parts, which can downsize an image processing system. If both the image processing unit and the image input/output unit includes a part capable of controlling a bus, the scope of operations performed by the image processing unit and the image input/output unit can be easily expanded by connecting the part to the bus.
However, in the first conventional example shown in FIG. 2A, since the image processing apparatus includes a plurality of image memories in order to process an image at a high speed, there is a large amount of hardware. Moreover, since it is necessary to indirectly accesses data in the image memory via the image processing unit when the CPU accesses data in the image memory, overhead is required to perform the access. This overhead makes it difficult to realize high-speed access to the image memory from the CPU. On the other hand, in the second conventional example shown in FIG. 2B, since the CPU, the image processing unit, and the image input/output unit all use the shared memory, there is a problem in that the load of the bus 2 shown in FIG. 2B becomes heavy. For example, if calculational processing of image data and input/output processing of picture data are executed in parallel, since the access to the image data and the picture data in the shared memory is performed via the bus 2, the load of the bus 2 is heavier than that in an image processing apparatus with an image memory exclusively used for image processing. That is, in the composition of the second conventional example, since the arbitration of the bus 2 is necessary, the overhead required for the arbitration of the bus 2 makes it difficult to increase the processing speed of the image processing apparatus when both the image processing unit and the image input/output unit frequently use the bus 2.
Furthermore, since the second conventional example shown in FIG. 2B does not possess a plurality of buses for the image processing unit and the image input/output unit to exclusively perform their respective access, various sets of image data cannot be processed in parallel. For example, feeding image data out of the shared memory to the image processing unit cannot be performed in parallel to sending the processed image data from the image processing unit to the shared memory. Accordingly, the processing speed is decreased in the second conventional example.
The present invention has been achieved in consideration of the above-described problems, and is aimed at providing an image processing apparatus in which a plurality of image processing functions is processed in parallel by realizing a method of efficient memory access, and the image processing can consequently be executed at a high speed.
To attain the above object, the present invention provides an image processing apparatus in which the main memory of a CPU is used as a shared memory, also functioning as an image memory, and image processing is performed by a plurality of function processing units, the image processing apparatus comprising:
a high priority function selection part for selecting functions, with the execution of each being required by a corresponding one of the function processing units, based on a predetermined priority for each of the functions; and
a data control unit including a data transfer part for preferentially accessing the shared memory, as required by the function selected by the high priority function selection part, and a plurality of data holding parts provided between the shared memory and the plurality of function processing units, with each of the plurality of data holding parts holding a predetermined amount of data which is processed by a corresponding one of the plurality of function processing units;
wherein each of the plurality of function processing units transmits with the data control unit separately from the others of the plurality of function processing units, and executes its function in parallel to the others of the plurality of function processing units. !!
Moreover, in the above image processing apparatus, the data control unit is connected to the CPU and the shared memory via a bus, and the data transfer part controls the bus connecting the CPU and the shared memory based on requirement for data transfer requested by each of the function processing units.
Furthermore, in the above image processing apparatus, each of the data holding parts includes a bit-width change function for changing both the bit-width of data transferred in the bus connecting the CPU and the shared memory and the bit-width of data processed by the function processing units, and transmits data with the bus in synchronization with the same operation clock as the clocks used for the bus, and data with the function processing units in synchronization with the same operation clock as the clocks used for the function processing units.
Additionally, in the above image processing apparatus, the data control unit simultaneously accesses image data of a plurality of pixels, stored in the shared memory, the number of the plurality of the image data corresponding to the bit-width of data stored in the shared memory.
Also, in the above image processing apparatus, the data transfer part reads multiple types of image data out of the shared memory by turns and sends the multiple types of image data to the plurality of data holding parts, and each of the plurality of data holding parts stores the image data sent to the data holding part and transmits image data with one of the function processing units independent of the others of the function processing units, the one being connected to the data holding part and executing image processing in parallel to the others of the function processing units.
Further, in the above image processing apparatus, sending of resultant data obtained by processing in each of the function processing units to a corresponding one of the data holding parts is performed in parallel to the inputting of the stored image data to the function processing unit from the one of the data holding parts.
Further still, in the above image processing apparatus, the data control unit and the plurality of function processing units are integrated in an integrated circuit formed in one silicon chip.
On the top of that, the present invention provides an image processing system in which a main memory of a CPU is used as a shared memory that is also used as an image memory, the image processing system comprising:
an image processor including a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on a predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts provided between the shared memory and the plurality of function processing units, each of the plurality of data holding parts holding a predetermined amount of data which are processed by a corresponding one of the plurality of function processing units, in which each of the plurality of function processing units transmits with the data control unit separately from the others of the plurality of function processing units, and executes its function in parallel to the others of the plurality of function processing units;
an image input unit connected to the image processor, to input data of an image;
wherein the shared memory stores image data input from the image input unit;
an image output unit connected to the image processor, to output data of an image obtained by processing in the image processor; and
buses for connecting the image processor, the CPU, and the shared memory.
In accordance with the present invention, it is possible to reduce the load of a bus connecting a main memory of a CPU and a plurality of function processing units used for image processing, by providing a plurality of data holding parts provided between the shared memory and the plurality of function processing units. Furthermore, since each of the plurality of data holding parts holds a predetermined amount of data which are to be processed by a corresponding one of the plurality of function processing units, each of the plurality of function processing units can execute its function in parallel to functions executed by the others of the function processing units.